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Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
FEATURES
* 20 LVCMOS outputs, 7 typical output impedance * 1 LVCMOS clock input * Maximum output frequency up to 250MHz * Bank enable logic allows unused banks to be disabled in reduced fanout applications * Output skew: 250ps (maximum) * Part-to-part skew: 600ps (maximum) * Bank skew: 200ps (maximum) * Multiple frequency skew: 300ps (maximum) * 3.3V or mixed 3.3V input, 2.5V output operating supply modes * 0C to 70C ambient operating temperature * Other divide values available on request
ICS8701
GENERAL DESCRIPTION
The ICS8701 is a low skew, /1, /2 Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
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The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS8701 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK /1 /2 DIV_SELA 1 QB0 - QB4 0 DIV_SELB 1 QC0 - QC4 0 DIV_SELC 1 QD0 - QD4 0 DIV_SELD nMR/OE BANK_EN0 BANK_EN1 Bank Enable Logic 1 QAO - QA4 0
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND
QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4
ICS8701
QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0
8701CY
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DIV_SELA DIV_SELB CLK GND VDD BANK_EN0 GND BANK_EN1 VDD nMR/OE DIV_SELC DIV_SELD
48-Pin LQFP 7mm x 7mm x 1.4mm Y Package Top View
REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
Type Power Description Output supply pins. Connect to 3.3V or 2.5V.
ICS8701
TABLE 1. PIN DESCRIPTIONS
Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 13 14 23 24 17, 19 15 Name VDDO
GND VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK DIV_SELD DIV_SELC DIV_SELB DIV_SELA BANK_EN1, BANK_EN0 nMR/OE
Power Power Output
Power supply ground. Connect to ground. Positive supply pins. Connect to 3.3V. Bank A outputs. LVCMOS interface levels. 7W typical output impedance. Bank B outputs. LVCMOS interface levels. 7W typical output impedance. Bank C outputs. LVCMOS interface levels. 7W typical output impedance. Bank D outputs. LVCMOS interface levels 7W typical output impedance. Pulldown LVCMOS / LVTTL clock input. Controls frequency division for bank D outputs. Pullup LVCMOS interface levels. Controls frequency division for bank C outputs. Pullup LVCMOS interface levels. Controls frequency division for bank B outputs. Pullup LVCMOS interface levels. Controls frequency division for bank A outputs. Pullup LVCMOS interface levels. Pullup Pullup Enables and disables outputs by banks. LVCMOS interface levels. Master reset and output enable. Enables and disables all outputs. LVCMOS interface levels.
Output
Output
Output Input Input Input Input Input Input Input
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
Test Conditions Minimum Typical Maximum 4 4 51 51 VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V 7 KW KW pF pF Units pF
ICS8701
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter CLK DIV_SELA, DIV_SELB, Input Capacitance DIV_SELC, DIV_SELD, BANK_EN0, NMR/OE, BANK_EN1, Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
CIN
RPULLUP RPULLDOWN CPD ROUT
W
TABLE 3. FUNCTION TABLE
Inputs nMR/OE 0 1 1 1 1 1 1 1 1 BANK_EN1 X 0 1 0 1 0 1 0 1 BANK_EN0 X 0 0 1 1 0 0 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0 - QA4 Hi Z Active Active Active Active Active Active Active Active QB0 - QB4 Hi Z Hi Z Active Active Active Hi Z Active Active Active Outputs QC0 - QC4 Hi Z Hi Z Hi Z Active Active Hi Z Hi Z Active Active QD0 - QD4 Hi Z Hi Z Hi Z Hi Z Active Hi Z Hi Z Hi Z Active Qx frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0lfpm) -65C to 150C
ICS8701
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 95 Units V V mA
VDD = VIH = 3.465V VIL = 0V
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK Test Conditions Minimum 2 2 VDD = 3.465V VDD = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA -150 -5 2.6 0.5 -0.3 -0.3 Typical Maximum 3.8 3.8 0.8 1.3 5 150 Units V V V V A A A A V V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH VOL
Output High Voltage Output Low Voltage
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
Test Conditions 0MHZ f 200MHz Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 30% to 70% 30% to 70% 0MHZ f 200MHz f = 200MHz 280 280 tCYCLE/2 - 0.5 2 Minimum 2.2 Typical Maximum 250 3.4 200 250 300 600 850 850 tCYCLE/2 + 0.5 3 Units MHz ns ps ps ps ps ps ps ns ns
ICS8701
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol fMAX tPD Parameter Maximum Input Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc tEN
tCYCLE/2 2.5
Output Enable Time; f = 10MHz 6 ns NOTE 6 Output Disable Time; f = 10MHz 6 ns tDIS NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the 50% point of the input to the output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the cross points. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 95 Units V V mA
ICS8701
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current
VDD = VIH = 3.465V VIL = 0V
TABLE 4D. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK Test Conditions Minimum 2 2 VDD = 3.465V VDD = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = 3.135V, VDDO = 2.375 IOH = -27mA VDD = 3.135V, VDDO = 2.375 IOL = 27mA -150 -5 1.8 -0.3 -0.3 Typical Maximum 3.8 3.8 0.8 1.3 5 150 Units V V V V A A A A V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
0.5
V
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
Test Conditions 0MHZ f 200MHz Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 30% to 70% 30% to 70% 0MHZ f 200MHz 280 280 tCYCLE/2 - 0.5 2 Minimum 2.6 Typical Maximum 250 3.6 225 250 300 600 850 850 tCYCLE/2 + 0.5 3 Units MHz ns ps ps ps ps ps ps ns
ICS8701
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Maximum Input Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc
tCYCLE/2
f = 200MHz 2.5 ns Output Enable Time; f = 10MHz 6 ns tEN NOTE 6 Output Disable Time; f = 10MHz 6 ns tDIS NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the 50% point of the input to the output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as the skew at between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the cross points. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
ICS8701
PARAMETER MEASUREMENT INFORMATION
VDD
VDDO
SCOPE LVCMOS
VDD = +1.65V VDDO = 1.65V
Qx
GND = -1.65V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
VDDO
SCOPE LVCMOS
Qx
VDDO = +1.25V
GND = -1.25V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
ICS8701
Qx
Qy
tsk(o)
FIGURE 2 - OUTPUT SKEW
PART 1 Qx
PART 2 Qy
tsk(pp)
FIGURE 3 - PART-TO-PART SKEW
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
80% 80% V 20% 20% t t
AND
SWING
ICS8701
Clock Inputs and Outputs
R
F
FIGURE 4 - INPUT
OUTPUT RISE
AND
FALL TIME
V
CLK
CC
/2
QAx, QBx, QCx, QDx
t
PD
FIGURE 5 - PROPAGATION DELAY
CLK, QAx, QBx, QCx, QDx
Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 6 - odc & tPERIOD
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR POWER CONSIDERATIONS
ICS8701
This section provides information on power dissipation and junction temperature for the ICS8701-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8701-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 20 * 32mW = 640mW
Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 640mW = 969.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.969W * 42.1C/W = 110.8C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 48-pin LQFP, Forced Convection
JA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
ICS8701
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVCMOS output driver circuit and termination are shown in Figure 7.
VDDO
Q1
VOUT RL 50
FIGURE 7 - LVCMOS DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
DD
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DD_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
* *
For logic high, V
OUT
=V
OH_MAX
=V
DD_MAX
- 1.2V - 0.4V
For logic low, V
OUT
=V
OL_MAX
=V
DD_MAX
Pd_H = (1.2V/50) * (2V - 1.2V) = 19.2mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR RELIABILITY INFORMATION
ICS8701
TABLE 7. JAVS. AIR FLOW TABLE
JA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8701 is: 1743
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
ICS8701
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
q
ccc
Reference Document: JEDEC Publication 95, MS-026
8701CY
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REV. B AUGUST 2, 2001
Integrated Circuit Systems, Inc.
LOW SKEW /1, /2 CLOCK GENERATOR
Marking ICS8701CY ICS8701CY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
ICS8701
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8701CY ICS8701CYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701CY
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REV. B AUGUST 2, 2001

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